Google Coral NPU reaches 32-bit completion with open standard for edge AI

What happened

Google Research announced three major milestones in the Coral NPU effort, a standards-based approach to unifying edge AI across fragmented hardware ecosystems. The complete 32-bit Coral NPU architecture is now finished, including the new Matrix Execution Unit. Alongside this, Google released Coral Compiler v1.0, an open-source end-to-end compiler and simulation stack based on IREE and MLIR. Synaptics simultaneously launched commercial silicon and developer kits built on Coral NPU technology: the 2nd-generation Astra SR200 series microcontroller (400 GOPS), the new Coralboard SR developer kit, and general availability of the Coralboard SL (1 TOPS) through DigiKey.

The architecture and compiler foundation

The 32-bit Coral NPU is a standards-based, ML-first RISC-V architecture designed to solve the fragmentation problem at the edge. Historically, edge accelerators chased high peak-compute specifications while leaving compiler teams to figure out software support afterward, causing unsupported neural network layers to fall back to general-purpose CPU and draining battery life. Coral NPU was designed with the compiler from the start, prioritizing energy-viable compute: delivering the right performance at the right power envelope.

The architecture consists of four completed milestones: a C-programmable RISC-V scalar frontend for control flow, an RVV v1.0 vector co-processor for SIMD operations, a tightly coupled memory subsystem with floating-point support, and the new Matrix Execution Unit. The Matrix Execution Unit addresses the inefficiency of running 2D matrix operations on 1D vector engines, which forces repeated loading of weights and activations from memory. Instead, it uses a dedicated outer-product multiply-accumulate engine that computes a full 2D tile of operations in a single cycle (256 MACs per cycle), reusing weights and activations in local registers. This configuration is tunable up to 1 TOPS with a target of 10mW average power for inference.

The Coral Compiler v1.0 takes models from JAX, PyTorch, or TensorFlow through standard representations like StableHLO and TOSA, then partitions workloads between the host CPU and Coral NPU core, handles operator fusion, tiles matrices to fit local SRAM, and lowers directly to Coral NPU scalar, RVV vector, and VME matrix instructions. Google provides the complete 32-bit RTL, an open-source MPACT simulator, and a reference FPGA design so teams can benchmark and tune configurations before fabrication.

Who it affects

This effort targets developers building wearables, industrial sensors, autonomous robots, and other edge devices that require low-latency inference, strict privacy, and all-day reliability without constant cloud connectivity. The architecture enables use cases like continuous multimodal workloads on battery-powered devices, real-time voice translation on wearables, spatial audio filtering on hearables, and low-latency visual perception on robots. Teams that previously had to rewrite kernels, re-quantize models, and debug vendor-specific compilers for each chip can now optimize a model once and deploy it across different SoC vendors, devices, and power envelopes. Silicon design teams benefit from the complete open design available on GitHub and partnerships with VeriSilicon for design implementation and verification, plus collaboration with GlobalFoundries on the 12LP+ FinFET process.

Commercial silicon and developer kits

Synaptics is bringing Coral NPU into commercial production across different power budgets. The 2nd-generation Synaptics Astra SR200 Series, taped out and launching this month, integrates Coral NPU IP including Milestone 2 RISC-V Vector Core support to deliver 400 GOPS in an ultra-low-power MCU package built for battery-powered wearables and industrial sensor nodes. The new Coralboard SR developer kit, powered by the Astra SR200 series, is designed for rapid prototyping of microcontroller-class edge and physical AI applications. The Coralboard SL, following its limited preview at Google I/O, is now generally available worldwide through DigiKey. Powered by the Astra SL2619 processor with a 1 TOPS Torq/Coral NPU subsystem, it brings transformer and multi-stream vision acceleration to Linux-based IoT and robotics. Because both product families build on the same architecture and compiler foundation, ML teams use the same workflow to deploy to a milliwatt-class wearable or a 1 TOPS board.

Getting started

Developers can access documentation and architecture guides at developers.google.com/coral. The complete 32-bit RTL, the v1.0 IREE/MLIR compiler stack, and the MPACT simulator are available on GitHub. The Synaptics Coralboard SL is available for order through DigiKey, and information on the Astra SR200 series and Coralboard SR is available on the Synaptics Coralboard Developer page. Google is already working on the next phase of the roadmap, including a 64-bit Coral NPU architecture and CHERI support for security.

Source

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